On The Design of Adiabatic SRAMs

In the design of low-power circuits, adiabatic logic shows great promise. However, research till date have concentrated on adiabatic logic circuits/families. Today's VLSlsystems integrate random logic, megamodules and memories. Hence, the success of adiabatic circuits will depend on the efficient implementation of not only random logic, but also the other components of a VLSI system. In this paper, we present a design of adiabatic Siaiic RAM, which can be implemerited withorit greatly increasing area or circuit complexity. The design addresses the issue of building ultra-low power memory circuits in a VLSI system. Our results for a 41<b block of memory core indicates energy savings of approximately 75% for both read and write operations. Higher power savings are achieved in the address decoder and 1/01 drivers. *The research was supported in part by NSF and by ARPA. A preliminary version of the paper appeared in the 1995 Low-Power Electronics Symposium.